The present invention relates to a gradation corrector used in correcting the gradation of a video signal in a television receiver, a video tape recorder or the like.
In recent years, great importance has been attached to a gradation corrector in order to provide a more clear image which is required with the increase in size of a color television receiver and the improvement in image quality thereof, and more especially, in order to expand the dynamic range of an image on a CRT by passing a video signal through a non-linear amplifier to correct the gradation of the video signal.
The present application is a parallel application Ser. No. 07/838,844 filed Feb. 21, 1992, with a preceding U.S. application entitled "Gradation Corrector" and filed by the present inventors on the basis of Japanese Patent Application No. 03-032792 and assigned to the same assignee with the present application. Both applications relate to improvements on gradation correctors and they are adapted to prevent correction oscillations due to noise and prevent response delays in sudden changes in video scene by detecting changes in the scene. In order for the improvement, the present improvement relies on a use of a recursive filter for flattening data stored in a histogram memory or data stored in a look-up table memory. The improvement by the preceding application invention relies on an arrangement of preventing oscillations of one of parameters used in histogram data conversion process which one parameter is of more significant influence to a resultant correction data.
FIG. 5 shows a block diagram of gradation corrector proposed precedently to the present application. In FIG. 5, reference numeral 1 designates an A/D converter for converting an input luminance signal into a digital value. Numeral 2 designates a histogram memory for obtaining a luminance distribution of the input luminance signal. In general, the luminance level enters an address of the memory 2 and the frequency enters as data thereof. Numeral 3 designates a histogram operating circuit for determining the mean value, the mode value, the minimum value, the maximum value, the deviation coefficient, the white area, the black area, etc. of the input luminance signal from the data of the histogram memory 2 and calculating control data of a limiter level, the value of addition, an accumulation start luminance level, an accumulation stop luminance level, the maximum output luminance level and so on from the determined values to output the control values to a limiter/adder circuit 5, an accumulation control register circuit 6 and a normalization control register circuit 7. On the basis of data transferred from the histogram operating circuit 3, the limiter/adder circuit 5 imposes a limitation on the data of the histogram so that it does not exceed a certain level and performs the operation of addition. In general, the data processing performed by the limiter/adder circuit 5 is completed during a time when the address is accessed once. The control data of the accumulation start and stop luminance levels, at which the accumulation is to be started and stopped in determining a cumulative histogram, are supplied from the histogram operating circuit 3 to the accumulation control register circuit 6 which in turn controls a histogram accumulation circuit 8. The histogram accumulation circuit 8 makes the accumulation of processed data from the histogram memory 2 on the basis of a control signal from the accumulation control register circuit 6. Numeral 9 designates a cumulative histogram memory for storing therein the result of accumulation by the histogram accumulation circuit 8. In general, the input luminance level enters an address of the memory 9 and a corrected output luminance level enters as data thereof. In normalizing data of the cumulative histogram to produce a look-up table, the maximum luminance level for an output luminance signal after normalization is supplied from the histogram operating circuit 3 to the normalization control register circuit 7 and the normalization control register circuit 7 controls a normalization coefficient in accordance with the value of the maximum luminance level. Numeral 10 designates a look-up table operating circuit which normalizes the data of the cumulative histogram memory 9 on the basis of an output signal of the normalization control register circuit 7. Numeral 11 designates a look-up table memory for storing therein the data normalized by the look-up table operating circuit 10. In general, the input luminance level enters an address of the memory 11 and the output luminance level enters as data thereof. Numeral 12 designates a timing control circuit which makes the sequencing of various operations and the control for the memories. Numeral 13 designates a D/A converter by which a output luminance signal in digital value corrected by use of the look-up table is converted into an analog value.
Next, explanation will be made of the operation of the gradation corrector having the above construction. FIGS. 6A to 6F show operating waveforms of various parts.
First, an input luminance signal a is inputted to the A/D converter 1 and is converted thereby into a digital value which is in turn outputted as a converted input luminance signal b. The converted input luminance signal b is taken as an address of the histogram memory 2 and data is processed by the limiter/adder circuit 5. By performing this operation during one vertical scanning interval, it is possible to obtain a histogram distribution of the input luminance signal a. The histogram distribution is shown in FIG. 6A.
Next, data of the histogram memory 2 including the histogram distribution is read by the histogram operating circuit 3 which in turn calculates the mean value, the mode value, the minimum value, the maximum value, the deviation coefficient, the white area, the black area, etc. of the input luminance signal. The histogram operating circuit 3 further determines the control data of the limiter level, the value of addition, an accumulation calculation start luminance level, an accumulation calculation stop luminance level, the maximum luminance level after normalization and so on from the result of the above calculation and transfers the determined data to control the limiter/adder circuit 5, the accumulation control register circuit 6 and the normalization control register circuit 7.
Thereafter, the limiter/adder circuit 5 reads data from the histogram memory 2 to make a limiter (see FIG. 6B) and the operation of addition or the like for each read data on the basis of each data transferred from the histogram operating circuit 3 and outputs the result (or corrected histogram data c) to the histogram accumulation circuit 8 (see FIG. 6C). In the case where the value of addition is fixed, a cumulative curve becomes nearer to a straight line as the value of addition is larger and approaches to a histogram flattening process as the value of addition is smaller (see FIGS. 6C and 6D).
On the basis of the accumulation start luminance level and the accumulation stop luminance level supplied from the accumulation control register circuit 6, the histogram accumulation circuit 8 calculates cumulative histogram data f for the corrected histogram data c in a range between the accumulation start and stop luminance levels and causes the cumulative histogram memory 9 to store the result of calculation.
Next, the look-up table operating circuit 10 reads the cumulative histogram data from the cumulative histogram memory 9 to determine a normalization coefficient so that the maximum value of the cumulative histogram data g becomes the maximum output luminance level h supplied from the normalization control register circuit 7. The look-up table operating circuit 10 performs an operation on all the cumulative histogram data g by use of the determined normalization coefficient and causes the look-up table memory 11 to store the result i. If the maximum output luminance level is controlled, an operation such as an automatic contrast control (ACL) or an automatic brightness control (ABL) is possible. Such an operation is shown in FIG. 6E.
Thereafter, data in the look-up table memory 11 is read with the converted input luminance signal b being used as an address and the read data is outputted as a corrected output luminance signal j. FIG. 6F shows a histogram of the corrected output luminance signal j. The D/A converter 13 outputs the corrected output luminance signal j after convertion thereof into an analog signal k.
The timing control circuit 12 controls the operations of various circuits so that the operations of respective parts are performed at such timings as mentioned above. (For example, refer to Japanese Patent Application No. (Hei)1-265393 (JP-A-3-126,377) entitled "Gradation Corrector" and filed by the applicant of the present application.)
In the above construction of the gradation corrector, however, since each control signal determined by the histogram operating circuit is an instantaneous value determined from the histogram distribution in one vertical scanning interval, there is a problem that the control signal value has a great variation due to noises or the like included in a video signal and the corrected output luminance signal oscillates as a result.